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LM3S1512_16 Datasheet, PDF (20/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller
Table of Contents
Register 2:
Register 3:
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Register 12:
Register 13:
Register 14:
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Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 439
UART Flag (UARTFR), offset 0x018 ................................................................................ 441
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 443
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 444
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 445
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 446
UART Control (UARTCTL), offset 0x030 ......................................................................... 448
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 450
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 452
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 454
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 455
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 456
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 458
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 459
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 460
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 461
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 462
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 463
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 464
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 465
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 466
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 467
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 468
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 469
Synchronous Serial Interface (SSI) ............................................................................................ 470
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 483
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 485
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 487
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 488
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 490
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 491
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 493
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 494
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 495
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 496
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 497
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 498
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 499
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 500
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 501
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 502
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 503
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 504
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 505
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 506
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 507
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 508
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 524
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July 15, 2014
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