LM3S1512_16 Datasheet, PDF (11/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Stellaris^® LM3S1512 Microcontroller
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 477
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 478
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 479
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 480
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 480
Figure 14-1. I²C Block Diagram ............................................................................................. 509
Figure 14-2. I²C Bus Configuration ........................................................................................ 510
Figure 14-3. START and STOP Conditions ............................................................................. 510
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 511
Figure 14-5. R/S Bit in First Byte ............................................................................................ 511
Figure 14-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 511
Figure 14-7. Master Single SEND .......................................................................................... 515
Figure 14-8. Master Single RECEIVE ..................................................................................... 516
Figure 14-9. Master Burst SEND ........................................................................................... 517
Figure 14-10. Master Burst RECEIVE ...................................................................................... 518
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 519
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 520
Figure 14-13. Slave Command Sequence ................................................................................ 521
Figure 15-1. Analog Comparator Module Block Diagram ......................................................... 546
Figure 15-2. Structure of Comparator Unit .............................................................................. 548
Figure 15-3. Comparator Internal Reference Structure ............................................................ 548
Figure 16-1. QEI Block Diagram ............................................................................................ 559
Figure 16-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 561
Figure 17-1. 100-Pin LQFP Package Pin Diagram .................................................................. 576
Figure 17-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 577
Figure 20-1. Load Conditions ................................................................................................ 610
Figure 20-2. JTAG Test Clock Input Timing ............................................................................. 613
Figure 20-3. JTAG Test Access Port (TAP) Timing .................................................................. 613
Figure 20-4. JTAG TRST Timing ............................................................................................ 613
Figure 20-5. External Reset Timing (RST) .............................................................................. 614
Figure 20-6. Power-On Reset Timing ..................................................................................... 614
Figure 20-7. Brown-Out Reset Timing .................................................................................... 615
Figure 20-8. Software Reset Timing ....................................................................................... 615
Figure 20-9. Watchdog Reset Timing ..................................................................................... 615
Figure 20-10. Hibernation Module Timing ................................................................................. 616
Figure 20-11. ADC Input Equivalency Diagram ......................................................................... 617
Figure 20-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 618
Figure 20-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 619
Figure 20-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 619
Figure 20-15. I²C Timing ......................................................................................................... 620
Figure D-1. Stellaris LM3S1512 100-Pin LQFP Package Dimensions ..................................... 648
Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 650
Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 651
Figure D-4. Stellaris LM3S1512 108-Ball BGA Package Dimensions ...................................... 652
Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 654
Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 655
July 15, 2014
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Texas Instruments-Production Data