LM3S1512_16 Datasheet, PDF (433/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Stellaris^® LM3S1512 Microcontroller
12.3.7
■ Overrun Error
■ Break Error
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 455).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 452) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 454).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 456).
The receive interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS
bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes
less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the
location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the
receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit.
The transmit interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger
level, the TXRIS bit is set. The transmit interrupt is based on a transition through level, therefore
the FIFO must be written past the programmed trigger level otherwise no further transmit interrupts
will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit.
■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 448). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
July 15, 2014
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