LM3S1512_16 Datasheet, PDF (12/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Revision History .................................................................................................. 22
Documentation Conventions ................................................................................ 29
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 52
Processor Register Map ....................................................................................... 53
PSR Register Combinations ................................................................................. 58
Memory Map ....................................................................................................... 66
Memory Access Behavior ..................................................................................... 68
SRAM Memory Bit-Banding Regions .................................................................... 70
Peripheral Memory Bit-Banding Regions ............................................................... 71
Exception Types .................................................................................................. 76
Interrupts ............................................................................................................ 77
Exception Return Behavior ................................................................................... 82
Faults ................................................................................................................. 83
Fault Status and Fault Address Registers .............................................................. 84
Cortex-M3 Instruction Summary ........................................................................... 86
Core Peripheral Register Regions ......................................................................... 89
Memory Attributes Summary ................................................................................ 92
TEX, S, C, and B Bit Field Encoding ..................................................................... 95
Cache Policy for Memory Attribute Encoding ......................................................... 96
AP Bit Field Encoding .......................................................................................... 96
Memory Region Attributes for Stellaris Microcontrollers .......................................... 96
Peripherals Register Map ..................................................................................... 97
Interrupt Priority Levels ...................................................................................... 122
Example SIZE Field Values ................................................................................ 150
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 154
JTAG_SWD_SWO Signals (108BGA) ................................................................. 155
JTAG Port Pins Reset State ............................................................................... 155
JTAG Instruction Register Commands ................................................................. 162
System Control & Clocks Signals (100LQFP) ...................................................... 166
System Control & Clocks Signals (108BGA) ........................................................ 166
Reset Sources ................................................................................................... 167
Clock Source Options ........................................................................................ 172
Possible System Clock Frequencies Using the SYSDIV Field ............................... 175
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 175
System Control Register Map ............................................................................. 179
RCC2 Fields that Override RCC fields ................................................................. 194
Hibernate Signals (100LQFP) ............................................................................. 234
Hibernate Signals (108BGA) .............................................................................. 235
Hibernation Module Register Map ....................................................................... 241
Flash Protection Policy Combinations ................................................................. 255
User-Programmable Flash Memory Resident Registers ....................................... 259
Flash Register Map ............................................................................................ 259
GPIO Pins With Non-Zero Reset Values .............................................................. 282
GPIO Pins and Alternate Functions (100LQFP) ................................................... 282
GPIO Pins and Alternate Functions (108BGA) ..................................................... 283
GPIO Signals (100LQFP) ................................................................................... 285
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July 15, 2014
Texas Instruments-Production Data