LM3S1512_16 Datasheet, PDF (19/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Stellaris^® LM3S1512 Microcontroller
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 373
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 374
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 375
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 376
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 377
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 378
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 379
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 380
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 381
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 382
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 383
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 384
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 385
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 386
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 387
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 388
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 389
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 390
Analog-to-Digital Converter (ADC) ............................................................................................. 391
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 401
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 402
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 403
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 404
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 405
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 406
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 409
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 410
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 412
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 413
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 414
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 416
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 419
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 419
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 419
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 419
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 420
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 420
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 420
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 420
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 421
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 421
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 422
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 422
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 424
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 425
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 426
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 427
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 437
July 15, 2014
19
Texas Instruments-Production Data