LM3S1512_16 Datasheet, PDF (562/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Quadrature Encoder Interface (QEI)
100 pulse per revolution encoder could use a load value of 82, resulting in 32,800 as the divisor,
which is 0.09% above 2¹⁴; in this case a shift by 15 would be an adequate approximation of the
divide in most cases. If absolute accuracy were required, the controller’s divide instruction could be
used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.
16.4
Initialization and Configuration
The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:
1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. Using a 1000-line encoder at four edges per line, there
are 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) since the
count is zero-based.
■ Write the QEICTL register with the value of 0x0000.0018.
■ Write the QEIMAXPOS register with the value of 0x0000.0F9F.
5. Enable the quadrature encoder by setting bit 0 of the QEICTL register.
6. Delay for some time.
7. Read the encoder position by reading the QEIPOS register value.
16.5
Register Map
Table 16-3 on page 562 lists the QEI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the module’s base address:
■ QEI0: 0x4002.C000
Note that the QEI module clock must be enabled before the registers can be programmed (see
page 214). There must be a delay of 3 system clocks after the QEI module clock is enabled before
any QEI module registers are accessed.
Table 16-3. QEI Register Map
Offset Name
Type
0x000 QEICTL
R/W
Reset
0x0000.0000
Description
QEI Control
See
page
564
562
July 15, 2014
Texas Instruments-Production Data