LM3S1512_16 Datasheet, PDF (592/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Signal Tables
Table 18-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
GNDA
B5
-
Power The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
B6
GND
-
Power Ground reference for logic and I/O pins.
PB5
I/O
TTL
GPIO port B bit 5.
B7
C1-
I
Analog Analog comparator 1 negative input.
PC2
I/O
TTL
GPIO port C bit 2.
B8
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
B9
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I/O
TTL
JTAG TMS and SWDIO.
B10
CMOD1
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
PE2
I/O
TTL
GPIO port E bit 2.
B11
SSI1Rx
I
TTL
SSI module 1 receive.
PE1
B12
SSI1Fss
I/O
TTL
GPIO port E bit 1.
I/O
TTL
SSI module 1 frame signal.
C1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
C4
GND
-
Power Ground reference for logic and I/O pins.
C5
GND
-
Power Ground reference for logic and I/O pins.
VDDA
C6
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 607, regardless of system implementation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 607, regardless of system implementation.
PH1
I/O
TTL
GPIO port H bit 1.
C8
CCP7
I/O
TTL
Capture/Compare/PWM 7.
PH0
I/O
TTL
GPIO port H bit 0.
C9
CCP6
I/O
TTL
Capture/Compare/PWM 6.
C10
PG7
I/O
TTL
GPIO port G bit 7.
PB2
C11
I2C0SCL
I/O
TTL
GPIO port B bit 2.
I/O
OD
I²C module 0 clock.
PB3
C12
I2C0SDA
I/O
TTL
GPIO port B bit 3.
I/O
OD
I²C module 0 data.
D1
PE4
I/O
TTL
GPIO port E bit 4.
592
July 15, 2014
Texas Instruments-Production Data