LM3S1512_16 Datasheet, PDF (110/660 Pages) Texas Instruments – Stellaris LM3S1512 Microcontroller

Cortex-M3 Peripherals
Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
Note: This register can only be accessed from privileged mode.
The UNPEND0 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 77 for interrupt assignments.
Interrupt 0-31 Clear Pending (UNPEND0)
Base 0xE000.E000
Offset 0x280
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
INT
Type
Reset Description
R/W 0x0000.0000 Interrupt Clear Pending
Value Description
0 On a read, indicates that the interrupt is not pending.
On a write, no effect.
1 On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
110
July 15, 2014
Texas Instruments-Production Data