DS90UB926Q-Q1 Datasheet, PDF (5/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

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DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
Pin Functions (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
MODE_SEL
15
I, Analog Device Configuration Select. See Table 9
IDx
56
I, Analog I2C Serial Control Bus Device ID Address Select
External pullup to V_DD33 is required under all conditions, DO NOT FLOAT.
Connect to external pullup and pulldown resistor to create a voltage divider.
See Figure 23
SCL
3
I/O,
I2C Clock Input / Output Interface
LVCMOS Must have an external pullup to V_DD33, DO NOT FLOAT.
Open-Drain Recommended pullup: 4.7 kΩ.
SDA
2
I/O,
I2C Data Input / Output Interface
LVCMOS Must have an external pullup to V_DD33, DO NOT FLOAT.
Open-Drain Recommended pullup: 4.7 kΩ.
BISTEN
44
I, LVCMOS BIST Enable Pin.
with pulldown 0: BIST Mode is disabled.
1: BIST Mode is enabled.
BISTC
16
I, LVCMOS BIST Clock Select.
with pulldown Shared with INTB_IN
0: PCLK; 1: 33 MHz
STATUS
LOCK
32
O, LVCMOS LOCK Status Output Pin
with pulldown 0: PLL is unlocked, ROUT[23:0]/RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states
are controlled by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
PASS
42
O, LVCMOS PASS Output Pin
with pulldown 0: One or more errors were detected in the received payload
1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
FPD-LINK III SERIAL INTERFACE
RIN+
49
I, LVDS True Input.
The interconnection should be AC-coupled to this pin with a 0.1-μF capacitor.
RIN-
50
I, LVDS Inverting Input.
The interconnection should be AC-coupled to this pin with a 0.1-μF capacitor.
CMLOUTP
52
O, LVDS True CML Output
Monitor point for equalized differential signal
CMLOUTN
53
O, LVDS Inverting CML Output
Monitor point for equalized differential signal
CMF
51
POWER AND GROUND⁽¹⁾
Analog Common Mode Filter. Connect 0.1-μF capacitor to GND
VDD33_A,
VDD33_B
48, 29
Power Power to on-chip regulator 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDD pin.
V_DDIO
13, 24, 38
Power
LVCMOS I/O Power 1.8 V ±5% OR 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDDIO
pin.
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPR12,
CAPP12,
CAPI2S
55, 57, 58
CAP
Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAP pin.
CAPL12
4
CAP
Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
OTHERS
NC
54
NC
No connect. This pin may be left open or tied to any level.
RES[1:0]
43.47
GND
Reserved. Tie to Ground.
(1) The VDD (V_DD33 and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
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