DS90UB926Q-Q1 Datasheet, PDF (17/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

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DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
Feature Description (continued)
The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps
maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.
7.3.2 Low-Speed Back Channel Data Transfer
The Low-Speed Backward Channel (LS_BC) of the DS90UB926Q-Q1 provides bidirectional communication
between the display and host processor. The information is carried back from the Deserializer to the Serializer
per serial symbol. The back channel control data is transferred over the single serial link along with the high-
speed forward data, DC balance coding and embedded clock information. This architecture provides a backward
path across the serial link together with a high-speed forward channel. The back channel contains the I2C, CRC
and 4 bits of standard GPIO information with 10-Mbps line rate.
7.3.3 Backward Compatible Mode
The DS90UB926Q-Q1 is also backward-compatible to DS90UR905Q and DS90UR907Q FPD Link II serializers
at 15 - 65 MHz pixel clock frequencies. It receives 28-bits of data over a single serial FPD-Link II pair operating
at the line rate of 420 Mbps to 1.82 Gbps. This backward compatible mode is provided through the MODE_SEL
pin (Table 9) or the configuration register (Table 11). In this mode, the minimum PCLK frequency is 15 MHz.
7.3.4 Input Equalization Gain
FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces the
medium-induced deterministic jitter. It equalizes up to 10-m STP cables with 3 connection breaks at maximum
serialized stream payload rate of 2.975 Gbps.
7.3.5 Common Mode Filter Pin (CMF)
The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1-μF capacitor has to be connected to this pin to Ground.
7.3.6 Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high-frequency
noise on the control signals. See Figure 13.
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