DS90UB926Q-Q1 Datasheet, PDF (12/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
ROUT[23:0]
t_XZR
Active to OFF Delay
(Figure 5)^{(1) (2)}
OEN = L, OSS_SEL = H
t_DDLT
t_DD
Lock Time (Figure 5)^{(3) (1) (2)} SSCG = OFF
Delay – Latency^{(1) (2)}
HS, VS, DE, PCLK,
LOCK, PASS
MCLK, I2S_CLK,
I2S_WC, I2S_DA,
I2S_DB
f = 5 – 85MHz
f = 5 – 85MHz
f = 5 – <15 MHz
t_DCCJ
Cycle-to-Cycle Jitter^{(1) (2)}
SSCG = OFF
f = 15 – 85 MHz
I2S_CLK = 1 -
12.28MHz
VDDIO = 1.71 - 1.89 V,
t_ONS
Data Valid After OEN = H
SetupTime (Figure 7)^{(1) (2)}
CL = 12pF
VDDIO = 3.0 – 3.6 V,
CL = 12pF
VDDIO = 1.71 - 1.89 V,
t_ONH
Data Tri-State After OEN = L ^{CL = 12pF}
SetupTime (Figure 7)^{(1) (2)}
VDDIO = 3.0 – 3.6 V,
CL = 12pF
VDDIO = 1.71 - 1.89 V,
Data Tri-State after OSS_
CL = 12pF
t_SES
SEL = H, Setup Time
(Figure 7)^{(1) (2)}
VDDIO = 3.0 – 3.6 V,
CL = 12pF
ROUT[23:0], HS, VS,
DE, PCLK, MCLK,
I2S_CLK, I2S_WC,
I2S_DA, I2S_DB
VDDIO = 1.71 - 1.89 V,
t_SEH
Data to Low after OSS_SEL
= L Setup Time (Figure 7)⁽¹⁾
(2)
CL = 12pF
VDDIO = 3.0 – 3.6 V,
CL = 12pF
MIN
TYP
10
15
60
5
147*T
0.5
0.2
±2
50
50
50
50
5
5
5
5
(1) Specification is ensured by characterization and is not tested in production.
(2) Specification is ensured by design and is not tested in production.
(3) t_DDLT is the time required by the device to obtain lock when exiting power-down state with an active serial stream.
PCLK
ROUT[n] (odd),
VS, HS
ROUT[n] (even),
DE
Figure 1. Checker Board Data Pattern
V_DDIO
GND
V_DDIO
GND
V_DDIO
GND
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MAX
UNIT
ns
ns
ns
40 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
EW
VOD (+)
CMLOUT
(Diff.)
EH
0V
EH
12
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VOD (-)
t_BIT (1 UI)
Figure 2. CML Output Driver
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