DS90UB926Q-Q1 Datasheet, PDF (23/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

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DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
F0L0
PD1
Cell Value 010
LSB=001
Frame = 0, Line = 0
Pixel Data one
R[7:2]+0, G[7:2]+1, B[7:2]+0
three lsb of 9 bit data (8 to 9 for Hi-Frc)
Pixel Index PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
LSLBS=B00=1001
F0L0
010
000
000
000
000
000
010
000
F0L1
101
000
000
000
101
000
000
000
F0L2
000
000
010
000
010
000
000
000
F0L3
000
000
101
000
000
000
101
000
F1L0
F1L1
F1L2
F1L3
000
000
000
000
000
000
000
000
000
111
000
000
000
111
000
000
000
000
000
000
000
000
000
000
000
000
000
111
000
000
000
111
F2L0
F2L1
F2L2
F2L3
000
000
010
000
010
000
000
000
000
000
101
000
000
000
101
000
010
000
000
000
000
000
010
000
101
000
000
000
101
000
000
000
F3L0
F3L1
F3L2
F3L3
000
000
000
000
000
000
000
000
000
000
000
111
000
000
000
111
000
000
000
000
000
000
000
000
000
111
000
000
000
111
000
000
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
Figure 16. Default FRC Algorithm
See Table 4 for recommended FRC settings dependant on 18/24–bit source, 18/24–bit white balance LUT, and
18/24–bit display.
Source
24–bit
24–bit
24–bit
18–bit
18–bit
18–bit
Table 4. Recommended FRC settings
White Balance LUT
24–bit
24–bit
18–bit
24–bit
24–bit
18–bit
Display
24–bit
18–bit
18–bit
24–bit
18–bit
18–bit
FRC1
Disabled
Disabled
Enabled
Disabled
Disabled
Disabled
FRC2
Disabled
Enabled
Disabled
Disabled
Enabled
Disabled
7.3.16 Internal Pattern Generation
The DS90UB926Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual
verification of panel operation. As long as the device is not in power down mode, the test pattern will be
displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a
programmed oscillator frequency. For detailed information, refer to Application Note AN-2198 (SNLA132).
7.3.17 Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics.
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