DS90UB926Q-Q1 Datasheet, PDF (15/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

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6.11 Typical Characteristics
DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
Time (1.25 ns/DIV)
Note: On the rising edge of each clock period, the CML driver
outputs a low Stop bit, high Start bit, and 33 DC-scrambled data
bits.
Figure 10. Serializer CML Driver Output
With 78-MHZ TX Pixel Clock
78 MHz TX
Pixel Clock
Input
(2 V/DIV)
78 MHz RX
Pixel Clock
Output
(2 V/DIV)
Time (10 ns/DIV)
Figure 11. Comparison of Deserializer LVCMOS RX PCLK
Output Locked to a 78-MHz TX PCLK
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