DS90UB926Q-Q1 Datasheet, PDF (21/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

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DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
2. Enable white balance
By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This
option may only be used after enabling the white balance reload feature through the associated serial control bus
register. In this mode the LUTs may be reloaded by the master controller through the I2C. This provides the user
with the flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT
values. The host controller loads the updated LUT values through the serial bus interface. There is no need to
disable the white balance feature while reloading the LUT data. Refreshing the white balance to the new set of
LUT data will be seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires that all 3 LUTs be loaded sequentially. When
reloading, partial LUT updates may be made.
8-bit in / 8 bit out
Gray level Data Out
Entry
(8-bits)
0 00000000b
1 00000001b
2 00000011b
3 00000011b
4 00000110b
5 00000110b
6 00000111b
7 00000111b
8 00001000b
9 00001010b
10 00001001b
11 00001011b
6-bit in / 6 bit out
Gray level Data Out
Entry
(8-bits)
0 00000000b
1 N/A
2 N/A
3 N/A
4 00000100b
5 N/A
6 N/A
7 N/A
8 00001000b
9 N/A
10 N/A
11 N/A
6-bit in / 8 bit out
Gray level Data Out
Entry
(8-bits)
0 00000001b
1 N/A
2 N/A
3 N/A
4 00000110b
5 N/A
6 N/A
7 N/A
8 00001011b
9 N/A
10 N/A
11 N/A
248 11111010b
249 11111010b
250 11111011b
251 11111011b
252 11111110b
253 11111101b
254 11111101b
255 11111111b
248 11111000b
249 N/A
250 N/A
251 N/A
252 11111100b
253 N/A
254 N/A
255 N/A
248 11111010b
249 N/A
250 N/A
251 N/A
252 11111111b
253 N/A
254 N/A
255 N/A
Figure 15. White Balance LUT Configurations
Table 3. White Balance Register Table
PAGE ADD
(dec)
0
42
ADD
(hex)
0x2A
Register Name
White Balance
Control
Bit(s) Access Default
(hex)
Function
7:6
RW
0x00 Page Setting
5
RW
4
RW
White Balance
Enable
3:0
1
0 – 00 – FF White Balance Red FF:0 RW
N/A
255
LUT
2
0 – 00 – FF White Balance
255
Green LUT
FF:0 RW
N/A
3
0 – 00 – FF White Balance
255
Blue LUT
FF:0 RW
N/A
Red LUT
Green LUT
Blue LUT
Description
00: Configuration Registers
01: Red LUT
10: Green LUT
11: Blue LUT
0: White Balance Disable
1: White Balance Enable
0: Reload Disable
1: Reload Enable
Reserved
256 8–bit entries to be applied to the Red
subpixel data
256 8–bit entries to be applied to the Green
subpixel data
256 8–bit entries to be applied to the Blue
subpixel data
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