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DS90UB926Q-Q1 Datasheet, PDF (33/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel
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DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
7.6 Register Maps
ADD
(dec)
0
ADD Register
(hex) Name
0x00 I2C Device ID
1 0x01 Reset
2 0x02 Configuration
[0]
Bit(s)
7:1
0
7
6:3
2
1
0
7
6
5
4
3
2
1
0
Table 11. Serial Control Bus Registers
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default Function
(hex)
Device ID
ID Setting
0x04
Remote
Auto Power
Down
BC Enable
Digital
RESET1
Digital
RESET0
0x00 Output
Enable
OEN and
OSS_SEL
Override
OSC Clock
Enable
Output
Sleep State
Select
(OSS_SEL)
Backward
Compatible
Mode
Override
Backward
Compatible
Mode
Select
LFMODE
Pin
Override
LFMODE
Descriptions
7–bit address of Deserializer
See Table 9
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
Remote Auto Power Down
1: Power down when no forward channel link is detected
0: Do not power down when no forward channel link is
detected
Reserved
Back channel enable
1: Enable
0: Disable
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
LVCMOS Output Enable.
1: Enable
0: Disable. Tri-state Outputs
Overrides Output Enable Pin and Output State pin
1: Enable override
0: Disable - no override
OSC Clock Output Enable
If loss of lock OSC clock is output onto PCLK
0: Disable
1: Enable
OSS Select to Control Output State during Lock Low
Period
1: Enable
0: Disable
Mode_Sel Backward compatible Mode Override Enable.
1: Use register bit "reg_02[2]" to set BC Mode
0: Use MODE_SEL option.
Backward Compatible Mode Select to DS90UR905Q and
DS90UR907Q. If Reg_02[3] = 1
1: Backward Compatible is on
0: Backward Compatible is off
LFMODE Pin Override Enable
1: Use register bit "reg_02[0]" to set LFMODE
0: Use LFMODE Pin
Low Frequency Mode Select
1: PCLK = 5 - <15 MHz
0: PCLK = 15 - 85 MHz
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