DS90UB926Q-Q1 Datasheet, PDF (28/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
www.ti.com
NO.
Description
1
Enable 18-bit
mode
2
GPIO3
3
GPIO2
4
GPIO1
5
GPIO0
Table 6. GPIO Enable Sequencing Table
Device
DS90UB925Q-Q1
DS90UB926Q-Q1
DS90UB925Q-Q1
DS90UB926Q-Q1
DS90UB925Q-Q1
DS90UB926Q-Q1
DS90UB925Q-Q1
DS90UB926Q-Q1
DS90UB925Q-Q1
DS90UB926Q-Q1
Forward Channel
0x12 = 0x04
Auto Load from DS90UB925Q-Q1
0x0F = 0x03
0x1F = 0x05
0x0E = 0x30
0x1E = 0x50
0x0E = 0x03
0x1E = 0x05
0x0D = 0x93
0x1D = 0x95
Back Channel
0x12 = 0x04
Auto Load from DS90UB925Q-Q1
0x0F = 0x05
0x1F = 0x03
0x0E = 0x50
0x1E = 0x30
0x0E = 0x05
0x0E = 0x05
0x0D = 0x95
0x1D = 0x93
GPO_REG[8:4] Enable Sequence
GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 7
for the GPO_REG enable sequencing.
1. Enable the 18-bit mode either through the configuration register bit Table 11 on DS90UB925Q-Q1 only.
DS90UB926Q-Q1 is automatically configured as in the 18-bit mode.
2. To enable GPO_REG8 outputs an “1” , write 0x90 to address 0x21 on DS90UB926Q-Q1.
NO.
Description
1
Enable 18-bit mode
2
GPO_REG8
3
GPO_REG7
4
GPO_REG6
5
GPO_REG5
6
GPO_REG4
Table 7. GPO_REG Enable Sequencing Table
Device
DS90UB926Q-Q1
DS90UB926Q-Q1
DS90UB926Q-Q1
DS90UB926Q-Q1
DS90UB926Q-Q1
DS90UB926Q-Q1
Local Access
0x12 = 0x04
(on DS90UB925Q-Q1)
0x21 = 0x90
0x21 = 0x10
0x21 = 0x09
0x21 = 0x01
0x20 = 0x90
0x20 = 0x10
0x20 = 0x09
0x20 = 0x01
0x1F = 0x90
0x1F = 0x10
Local Output Value
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
7.4 Device Functional Modes
7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the DS90UB926Q-Q1 completes its lock sequence to the
input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input
is available on the parallel bus and PCLK outputs. The State of the outputs are based on the OEN and
OSS_SEL setting (Table 8) or register bit (Table 11). See Figure 7.
Table 8. Output States
INPUTS
Serial
input
X
X
X
PDB
0
1
1
OEN
X
0
0
OUTPUTS
OSS_SEL Lock
X
Z
0
L or H
1
L or H
Pass
Z
L
Z
Data, GPIO, I2S
CLK
Z
Z
L
L
Z
Z
28
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