DS90UB926Q-Q1 Datasheet, PDF (47/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

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Typical Application (continued)
DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
HOST
Graphics
Processor
V_DDIO V_DD33
(1.8V or 3.3V) (3.3V)
V_DD33 V_DDIO
(3.3V) (1.8V or 3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
I2S AUDIO ³
(STEREO)
SCL
SDA
IDx
DOUT+
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
DOUT-
DS90UB925Q-Q1
Serializer
DAP
100: STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UB926Q-Q1
Deserializer
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
RGB Display
720p
24-bit color depth
3 _{I2S AUDIO}
(STEREO)
MCLK
DAP
Figure 25. Typical Display System Diagram
Figure 24 shows a typical application of the DS90UB926Q-Q1 deserializer for an 85-MHz, 24-bit Color Display
Application. Inputs use 0.1-μF coupling capacitors to the line and the deserializer provides internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1-μF capacitors and two 4.7-
μF capacitors should be used for local device bypassing. Ferrite beads are placed on the power lines for
effective noise suppression. Since the device in the Pin/STRAP mode, two 10-kΩ pullup resistors are used on
the parallel output bus to select the desired device features.
The interface to the target display is with 3.3-V LVCMOS levels, thus the V_DDIO pins are connected to the 3.3-V
rail. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
8.2.1 Design Requirements
For the typical design application, use the following as input parameters.
Table 12. Design Parameters
DESIGN PARAMETER
VDDIO
VDD33
AC Coupling Capacitor for RIN±
PCLK Frequency
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
100 nF
78 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Transmission Media
The DS90UB925Q-Q1 and DS90UB926Q-Q1 chipset is intended to be used in a point-to-point configuration
through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize
impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should
have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the
quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical
environment (e.g. power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application
environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye-opening width and eye-opening height. A differential probe should be used to measure
across the termination resistor at the CMLOUTP/N pin Figure 2.
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