DS90UB926Q-Q1 Datasheet, PDF (49/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

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DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
Layout Guidelines (continued)
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML
lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are
typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will
appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.
Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
DEVICE
Table 13. No Pullback WQFN Stencil Aperture Summary
PIN MKT Dwg
COUNT
PCB I/O
Pad Size
(mm)
PCB
PITCH
(mm)
PCB DAP
SIZE (mm)
STENCIL I/O
APERTURE
(mm)
STENCIL DAP
Aperture (mm)
DS90UB926Q-
Q1
60
NKB0060B 0.25 x 0.6
0.5
6.3 x 6.3
0.25 x 0.8
6.3 x 6.3
NUMBER of
DAP
APERTURE
OPENINGS
1
Figure 28 shows the PCB layout example derived from the layout design of the DS90UB926QSEVB Evaluation
Board. The graphic and layout description are used to determine both proper routing and proper solder
techniques when designing the Serializer board.
10.1.1 CML Interconnect Guidelines
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100-Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500-Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds.
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