DS90UB926Q-Q1 Datasheet, PDF (1/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

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DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
DS90UB926Q-Q1 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional
Control Channel
1 Features
•1 Bidirectional Control Interface Channel Interface
With I²C Compatible Serial Control Bus
• Supports High-Definition (720p) Digital Video
Format
• RGB888 + VS, HS, DE and Synchronized I2S
Audio Supported
• 5- to 85-MHz PCLK Supported
• Single 3.3-V Operation With 1.8-V or 3.3-V
Compatible LVCMOS I/O Interface
• AC-Coupled STP Interconnect up to 10 Meters
• Parallel LVCMOS Video Outputs
• I²C Compatible Serial Control Bus for
Configuration
• DC-balanced and Scrambled Data With
Embedded Clock
• Adaptive Cable Equalization
• Supports Repeater Application
• @ SPEED Link BIST Mode and LOCK Status Pin
• Image Enhancement (White Balance and
Dithering) and Internal Pattern Generation
• EMI Minimization (SSCG and EPTO)
• Low Power Modes Minimize Power Dissipation
• Automotive-Grade Product: AEC-Q100 Grade 2
Qualified
• Greater than 8 kV HBM and ISO 10605 ESD
Rating
• Backward Compatible to FPD-Link II
2 Applications
• Automotive Display for Navigation
• Rear Seat Entertainment Systems
• Automotive Drive Assistance
• Automotive Megapixel Camera Systems
3 Description
The DS90UB926Q-Q1 deserializer, in conjunction
with the DS90UB925Q-Q1 serializer, provides a
complete digital interface for concurrent transmission
of high-speed video, audio, and control data for
automotive display and image-sensing applications.
This chipset translates a parallel RGB video interface
into a single-pair high-speed serialized interface. The
serial bus scheme, FPD-Link III, supports full duplex
of high-speed forward data transmission and low-
speed backchannel communication over a single
differential link. Consolidation of video data and
control over a single differential pair reduces the
interconnect size and weight, while also eliminating
skew issues and simplifying system design.
The DS90UB926Q-Q1 deserializer recovers the RGB
data, three video control signals, and four
synchronized I2S audio signals. The device extracts
the clock from a high-speed serial stream. An output
LOCK pin provides the link status if the incoming data
stream is locked, without the use of a training
sequence or special SYNC patterns, as well as a
reference clock.
The DS90UB926Q-Q1 deserializer has a 31-bit
parallel LVCMOS output interface to accommodate
the RGB, video control, and audio data.
An adaptive equalizer optimizes the maximum cable
reach. EMI is minimized by output SSC generation
(SSCG) and enhanced progressive turnon (EPTO)
features.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UB926Q-Q1 WQFN (60)
9.00 mm x 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
HOST
Graphics
Processor
VDDIO VDD33
(1.8V or 3.3V) (3.3V)
VDD33 VDDIO
(3.3V) (1.8V or 3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
I2S AUDIO ³
(STEREO)
SCL
SDA
IDx
DOUT+
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
DOUT-
DS90UB925Q-Q1
Serializer
DAP
100: STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UB926Q-Q1
Deserializer
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
RGB Display
720p
24-bit color depth
3
I2S AUDIO
(STEREO)
MCLK
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.