DS90UB926Q-Q1 Datasheet, PDF (16/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
7 Detailed Description
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7.1 Overview
The DS90UB926Q-Q1 deserializer receives a 35-bits symbol over a single serial FPD-Link III pair operating up to
2.975-Gbps application payload. The serial stream contains an embedded clock, video control signals and the
DC-balanced video data and audio data which enhance signal quality to support AC coupling.
The DS90UB926Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. The recovered parallel LVCMOS video bus is then provided to the display. The deserializer is intended
for use with the DS90UB925Q-Q1 serializer, but is also backward-compatible with DS90UR905Q or
DS90UR907Q FPD-Link II serializer.
7.2 Functional Block Diagram
CMF
RIN+
RIN-
CMLOUTP
CMLOUTN
BISTEN
BISTC
PDB
SCL
SCA
IDx
MODE_SEL
REGULATOR
SSCG
Timing and
Control
Error
Detector
Clock and
Data
Recovery
24
ROUT [23:0]
HS
VS
DE
4 I2S_CLK
I2S_WC
I2S_DA
MCLK
PASS
PCLK
LOCK
DS90UB926Q-Q1 Deserializer
7.3 Feature Description
7.3.1 High-Speed Forward Channel Data Transfer
The High-Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or
YUV data, sync signals, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 12 illustrates the
serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC-coupled link.
Data is randomized, balanced and scrambled.
C1
C0
Figure 12. FPD-Link III Serial Stream
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