DS90UB926Q-Q1 Datasheet, PDF (44/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
www.ti.com
Register Maps (continued)
ADD
(dec)
101
ADD Register
(hex) Name
0x65 Pattern
Generator
Configuration
102 0x66 Pattern
Generator
Indirect
Address
103 0x67 Pattern
Generator
Indirect Data
240 0xF0 RX ID
241 0xF1
242 0xF2
243 0xF3
244 0xF4
245 0xF5
Table 11. Serial Control Bus Registers (continued)
Bit(s)
7:5
4
3
2
1
0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Register
Type
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
Default Function
(hex)
0x00
Pattern
Generator
18 Bits
Pattern
Generator
External
Clock
Pattern
Generator
Timing
Select
Pattern
Generator
Color Invert
Pattern
Generator
Auto-Scroll
Enable
0x00 Indirect
Address
0x00 Indirect
Data
0x5F ID0
0x55 ID1
0x48 ID2
0x39 ID3
0x32 ID4
0x36 ID5
Descriptions
Reserved
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled patterns
will have 64 levels of brightness and the R, G, and B
outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use
256 levels of brightness.
Select External Clock Source
1: Selects the external pixel clock when using internal
timing.
0: Selects the internal divided clock when using internal
timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
Timing Select Control
1: The Pattern Generator creates its own video timing as
configured in the Pattern Generator Total Frame Size,
Active Frame Size. Horizontal Sync Width, Vertical Sync
Width, Horizontal Back Porch, Vertical Back Porch, and
Sync Configuration registers.
0: the Pattern Generator uses external video timing from
the pixel clock, Data Enable, Horizontal Sync, and Vertical
Sync signals.
Enable Inverted Color Patterns
1: Invert the color output.
0: Do not invert the color output.
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the
next enabled pattern after the number of frames specified
in the Pattern Generator Frame Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
This 8-bit field sets the indirect address for accesses to
indirectly-mapped registers. It should be written prior to
reading or writing the Pattern Generator Indirect Data
register.
See AN-2198 (SNLA132)
When writing to indirect registers, this register contains the
data to be written. When reading from indirect registers,
this register contains the read back value.
See AN-2198 (SNLA132
First byte ID code: _
Second byte of ID code: U
Third byte of ID code, Value will be either B.
Fourth byte of ID code: 9
Fifth byte of ID code: 2
Sixth byte of ID code: 6
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