DS90UB926Q-Q1 Datasheet, PDF (11/57 Pages) Texas Instruments – 5- to 85-MHz 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

www.ti.com
6.9 Timing Requirements for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
f_SCL
t_LOW
t_HIGH
t_HD;STA
t_SU:STA
t_HD;DAT
t_SU;DAT
t_SU;STO
t_BUF
t_r
t_f
SCL Clock Frequency
SCL Low Period
SCL High Period
Hold time for a start or a
repeated start condition
(Figure 9)
Set Up time for a start or a
repeated start condition
(Figure 9)
Data Hold Time (Figure 9)
Data Set Up Time (Figure 9)
Set Up Time for STOP
Condition (Figure 9)
Bus Free Time between STOP
and START (Figure 9)
SCL & SDA Rise Time
(Figure 9)
SCL & SDA Fall Time
(Figure 9)
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast mode
DS90UB926Q-Q1
SNLS422B – JULY 2012 – REVISED JANUARY 2015
MIN NOM MAX UNIT
0
100 kHz
0
400 kHz
4.7
µs
1.3
µs
4.0
µs
0.6
µs
4.0
µs
0.6
µs
4.7
µs
0.6
µs
0
3.45 µs
0
0.9 µs
250
ns
100
ns
4.0
µs
0.6
µs
4.7
µs
1.3
µs
1000 ns
300 ns
300 ns
300 ns
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
t_RCP
t_RDC
t_CLH
t_CHL
t_ROS
t_ROH
PCLK Output Period
PCLK Output Duty Cycle
t_RCP = t_TCP
LVCMOS Low-to-High
Transition Time (Figure 3)
LVCMOS High-to-Low
Transition Time (Figure 3)
Data Valid before PCLK –
Setup Time
SSCG = OFF (Figure 6)
Data Valid after PCLK – Hold
Time
SSCG = OFF (Figure 6)
V_DDIO = 1.71 - 1.89 V,
C_L = 12pF
V_DDIO = 3.0 – 3.6 V,
C_L = 12pF
V_DDIO = 1.71 - 1.89 V,
C_L = 12pF
V_DDIO = 3.0 – 3.6 V,
C_L = 12pF
V_DDIO = 1.71 - 1.89 V,
C_L = 12pF
V_DDIO = 3.0 – 3.6 V,
C_L = 12pF
V_DDIO = 1.71 - 1.89 V,
C_L = 12pF
V_DDIO = 3.0 – 3.6 V,
C_L = 12pF
PCLK
ROUT[23:0], HS, VS,
DE, PCLK, LOCK,
PASS, MCLK,
I2S_CLK, I2S_WC,
I2S_DA, I2S_DB
MIN
11.76
45%
2.2
2.2
3.0
3.0
TYP
T
50%
2
2
2
2
MAX
200
55%
3
UNIT
ns
ns
3 ns
3 ns
3 ns
ns
ns
ns
ns
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
Submit Documentation Feedback
11