DS90UH926Q-Q1 Datasheet, PDF (49/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

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8.2.3 Application Curves
DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
Time (100 ps/DIV)
Figure 26. Deserializer CMLOUT Eye Diagram With 78-MHz
TX Pixel Clock
Time (2.5 ns/DIV)
Figure 27. Deserializer FPD-Link III Input With 78-MHz TX
Pixel Clock
9 Power Supply Recommendations
This section describes the power-up requirements and the PDB pin. The VDDs (V₃₃ and V_DDIO) supply ramp
should be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin is needed to ensure PDB
arrives after all the VDDs have settled to the recommended operating voltage. When PDB pin is pulled to V_DDIO =
3.0 V to 3.6 V or V_DD33, it is recommended to use a 10-kΩ pullup and a >10-uF cap to GND to delay the PDB
input signal.
All inputs must not be driven until V_DD33 and V_DDIO has reached its steady-state value.
10 Layout
10.1 Layout Guidelines
Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high-frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50 µF to 100 µF range and will smooth low-frequency switching noise. TI
recommends connecting the power and ground pins directly to the power and ground planes with bypass
capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body
size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
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