DS90UH926Q-Q1 Datasheet, PDF (11/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

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DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_XZR
Active to OFF Delay
Figure 5 ^{(1) (2)}
OEN = L, OSS_SEL = H
t_DDLT
t_DD
Lock Time
Figure 5 ^{(1) (2) (3)}
Delay – Latency^{(1) (2)}
t_DCCJ
Cycle-to-Cycle Jitter^{(1) (2)}
SSCG = OFF
SSCG = OFF
t_ONS
Data Valid After OEN = H
SetupTime
Figure 7 ^{(1) (2)}
VDDIO = 1.71 - 1.89 V,
CL = 12pF
VDDIO = 3.0 – 3.6 V,
CL = 12pF
t_ONH
Data Tri-State After OEN = L
SetupTime
Figure 7 ^{(1) (2)}
VDDIO = 1.71 - 1.89 V,
CL = 12pF
VDDIO = 3.0 – 3.6 V,
CL = 12pF
VDDIO = 1.71 - 1.89 V,
Data Tri-State after OSS_ SEL = _{CL = 12pF}
t_SES
H, Setup Time
Figure 7 ^{(1) (2)}
VDDIO = 3.0 – 3.6 V,
CL = 12pF
VDDIO = 1.71 - 1.89 V,
Data to Low after OSS_SEL = L _{CL = 12pF}
t_SEH
Setup Time
Figure 7 ^{(1) (2)}
VDDIO = 3.0 – 3.6 V,
CL = 12pF
PIN/FREQ.
R[7:0], G[7:0],
B[7:0]
HS, VS, DE,
PCLK, LOCK,
PASS
MCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
f = 5 – 85MHz
f = 5 – 85MHz
f = 5 – <15
MHz
f = 15 – 85
MHz
I2S_CLK = 1 -
12.28MHz
R[7:0], G[7:0],
B[7:0], HS,
VS, DE,
PCLK, MCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
MIN TYP
10
15
60
5
147*T
0.5
0.2
±2
50
50
50
50
5
5
5
5
(1) Specification is ensured by characterization and is not tested in production.
(2) Specification is ensured by design and is not tested in production.
(3) t_DDLT is the time required by the device to obtain lock when exiting power-down state with an active serial stream.
MAX UNIT
ns
ns
ns
40 ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PCLK
RGB[n] (odd),
VS, HS
RGB[n] (even),
DE
Figure 1. Checker Board Data Pattern
V_DDIO
GND
V_DDIO
GND
V_DDIO
GND
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