DS90UH926Q-Q1 Datasheet, PDF (27/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

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DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
7.4 Device Functional Modes
7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the DS90UH926Q-Q1 completes its lock sequence to the
input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input
is available on the parallel bus and PCLK outputs. The State of the outputs are based on the OEN and
OSS_SEL setting (Table 8) or register bit (Table 11). See Figure 7.
INPUTS
Serial
input
X
X
X
Static
PDB
0
1
1
1
Static
1
Active
1
Active
1
OEN
X
0
0
1
1
1
1
Table 8. Output States
OUTPUTS
OSS_SEL Lock
Pass
Data, GPIO, I2S
X
Z
Z
Z
0
L or H
L
L
1
L or H
Z
Z
0
L
L
L
1
L
0
H
1
H
Previous Status
L
Valid
L
L
Valid
CLK
Z
L
Z
L/OSC (Register bit
enable)
L
L
Valid
7.4.2 Low Frequency Optimization (LFMODE)
The LFMODE is set through a register (Table 11) or MODE_SEL Pin 24 (Table 9). It controls the operating
frequency of the deserializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz.
If LFMODE is High, the PCLK frequency is between 5 MHz and <15 MHz. Please note: when the device
LFMODE is changed, a PDB reset is required.
7.4.3 Configuration Select (MODE_SEL)
Configuration of the device may be done through the MODE_SEL input pin, or through the configuration register
bit. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the
MODE_SEL input (V_R4) and V_DD33 to select one of the other 10 possible selected modes. See Figure 19 and
Table 9.
VDD33
R₃
VR4
R₄
MODE_SEL
DES
Figure 19. MODE_SEL Connection Diagram
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