DS90UH926Q-Q1 Datasheet, PDF (1/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
DS90UH926Q-Q1 720p 24-Bit Color FPD-Link III Deserializer With HDCP
1 Features
•1 Integrated HDCP Cipher Engine with On-Chip Key
Storage
• Bidirectional Control Interface Channel Interface
with I²C Compatible Serial Control Bus
• Supports High-Definition (720p) Digital Video
Format
• RGB888 + VS, HS, DE and I2S Audio Supported
• 5- to 85-MHz PCLK Supported
• Single 3.3-V Operation With 1.8-V or 3.3-V
Compatible LVCMOS I/O Interface
• AC-Coupled STP Interconnect up to 10 Meters
• Parallel LVCMOS Video Outputs
• DC-Balanced and Scrambled Data With
Embedded Clock
• Adaptive Cable Equalization
• Supports HDCP Repeater Application
• Image Enhancement (White Balance and
Dithering) and Internal Pattern Generation
• EMI Minimization (SSCG and EPTO)
• Low Power Modes Minimize Power Dissipation
• Automotive-Grade Product: AEC-Q100 Grade 2
Qualified
• Greater Than 8 kV HBM and ISO 10605 ESD
Rating
• Backward-Compatible Modes
2 Applications
• Automotive Display for Navigation
• Rear Seat Entertainment Systems
3 Description
The DS90UH926Q-Q1 deserializer, in conjunction
with the DS90UH925Q-Q1 serializer, provides a
solution for secure distribution of content-protected
digital video within automotive entertainment
systems. This chipset translates a parallel RGB video
interface into a single-pair high-speed serialized
interface. The digital video data is protected using the
industry standard HDCP copy protection scheme.
The serial bus scheme, FPD-Link III, supports full
duplex of high-speed forward data transmission and
low-speed backchannel communication over a single
differential link. Consolidation of video data and
control over a single differential pair reduces the
interconnect size and weight, while also eliminating
skew issues and simplifying system design.
The DS90UH926Q-Q1 deserializer has a 31-bit
parallel LVCMOS output interface to accommodate
the RGB, video control, and audio data. The device
extracts the clock from a high-speed serial stream.
An output LOCK pin provides the link status if the
incoming data stream is locked, without the use of a
training sequence or special SYNC patterns, as well
as a reference clock.
An adaptive equalizer optimizes the maximum cable
reach. EMI is minimized by output SSC generation
(SSCG) and enhanced progressive turnon (EPTO)
features.
The HDCP cipher engine is implemented in both the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UH926Q-Q1 WQFN (60)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Diagram
V_DDIO VDD33
(1.8V or 3.3V) (3.3V)
VDD33 VDDIO
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
3
I2S AUDIO _/
(STEREO)
SCL
SDA
IDx
DOUT+
FPD-Link III
1 Pair /AC Coupled
0.1 2F
0.1 2F
DOUT-
DS90UH925Q-Q1
Serializer
DAP
100 ohm STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UH926Q-Q1
Deserializer
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
RGB Display
720p
24-bit color depth
3
/
I2S AUDIO
(STEREO)
MCLK
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.