DS90UH926Q-Q1 Datasheet, PDF (15/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

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7 Detailed Description
DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
7.1 Overview
The DS90UH926Q-Q1 deserializer receives a 35-bits symbol over a single serial FPD-Link III pair operating up
to a 2.975-Gbps application payload. The serial stream contains an embedded clock, video control signals and
the DC-balanced video data and audio data which enhance signal quality to support AC coupling.
The DS90UH926Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. It also applies decryption through a High-Bandwidth Digital Content Protection (HDCP) Cipher to this
video and audio data stream following reception of the data from the FPD-Link III decoder. The decrypted parallel
LVCMOS video bus is provided to the display. The deserializer is intended for use with the DS90UH925Q
serializer, but is also backward-compatible with DS90UR905Q or DS90UR907Q FPD-Link II serializer.
7.2 Functional Block Diagram
CMF
RIN+
RIN-
CMLOUTP
CMLOUTN
BISTEN
BISTC
PDB
SCL
SCA
IDx
MODE_SEL
REGULATOR
SSCG
Timing and
Control
Error
Detector
Clock and
Data
Recovery
24
RGB [7:0]
HS
VS
DE
4
I2S_CLK
I2S_WC
I2S_DA
MCLK
PASS
PCLK
LOCK
7.3 Feature Description
7.3.1 High-Speed Forward Channel Data Transfer
The High-Speed Forward Channel (HS_FC) is composed of 35 bits of data containing RGB data, sync signals,
HDCP, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 12 illustrates the serial stream per
PCLK cycle. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,
balanced and scrambled.
C1
C0
Figure 12. FPD-Link III Serial Stream
The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps
maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.
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