DS90UH926Q-Q1 Datasheet, PDF (4/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
www.ti.com
Pin Functions (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
HS
8
O, LVCMOS Horizontal Sync Output Pin
with pulldown Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 11
VS
7
O, LVCMOS Vertical Sync Output Pin
with pulldown Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
DE
6
O, LVCMOS Data Enable Output Pin
with pulldown Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 11
PCLK
5
O, LVCMOS Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 11
with pulldown
I2S_CLK,
I2S_WC,
I2S_DA
1, 30, 45
O, LVCMOS Digital Audio Interface Data Output Pins
with pulldown Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
MCLK
60
O, LVCMOS I2S Master Clock Output. x1, x2, or x4 of I2S_CLK Frequency.
with pulldown
OPTIONAL PARALLEL INTERFACE
I2S_DB
18
O, LVCMOS Second Channel Digital Audio Interface Data Output pin at 18–bit color mode and set by
with pulldown MODE_SEL or configuration register
Leave open if unused
I2S_B can optionally be used as BI or GPO_REG5.
GPIO[3:0]
27, 28, 40, 41
I/O,
Standard General Purpose IOs.
LVCMOS Available only in 18-bit color mode, and set by MODE_SEL or configuration register.
with pulldown See Table 11
Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[8: 1, 30, 45, 18, O, LVCMOS General Purpose Outputs and set by configuration register. See Table 11
4]
19
with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
INTB_IN
16
Input, Interrupt Input
LVCMOS Shared with BISTC
with pulldown
CONTROL
PDB
59
I, LVCMOS Power-down Mode Input Pin
with pulldown PDB = H, device is enabled (normal operation)
Refer to .
PDB = L, device is powered down.
When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE,
the PLL is shutdown and IDD is minimized. .
OEN
31
Input, Output Enable Pin.
LVCMOS See Table 8
with pulldown
OSS_SEL
46
Input, Output Sleep State Select Pin.
LVCMOS See Table 8
with pulldown
MODE_SEL
15
I, Analog Device Configuration Select. See Table 9
BISTEN
44
I, LVCMOS BIST Enable Pin.
with pulldown 0: BIST Mode is disabled.
1: BIST Mode is enabled.
BISTC
16
I, LVCMOS BIST Clock Select.
with pulldown Shared with INTB_IN
0: PCLK; 1: 33 MHz
4
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS90UH926Q-Q1