DS90UH926Q-Q1 Datasheet, PDF (40/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
www.ti.com
Register Maps (continued)
ADD
(dec)
36
37
38
39
41
42
ADD Register
(hex) Name
0x24 BIST Control
0x25 BIST Error
0x26 SCL High
Time
0x27 SCL Low Time
0x29 FRC Control
0x2A White Balance
Control
Table 11. Serial Control Bus Registers (continued)
Bit(s)
7:4
3
2:1
0
7:0
7:0
7:0
7
6
5
4
3
2
1
0
7:6
5
4
3:0
Register
Type
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default Function
(hex)
Descriptions
0x08
Reserved
BIST Pin
Config
BIST Configured through Pin
1: BIST configured through pin
0: BIST configured through register bit
BIST Clock
Source
BIST Clock Source
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
BIST
Enable
BIST Control
1: Enabled
0: Disabled
0x00 BIST Error BIST Error Count
Count
0x83 SCL High
Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL output
when the Deserializer is the Master on the local I2C bus.
Units are 50 ns for the nominal oscillator clock frequency.
The default value is set to provide a minimum 5us SCL
high time with the internal oscillator clock running at
26MHz rather than the nominal 20MHz.
0x84 SCL Low
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL output
when the De-Serializer is the Master on the local I2C bus.
This value is also used as the SDA setup time by the I2C
Slave for providing data prior to releasing SCL during
accesses over the Bidirectional Control Channel. Units are
50 ns for the nominal oscillator clock frequency. The
default value is set to provide a minimum 5us SCL low
time with the internal oscillator clock running at 26MHz
rather than the nominal 20MHz.
0x00
Timing
Mode
Select
Select display timing mode
0: DE only Mode
1: Sync Mode (VS,HS)
VS Polarity 0: Active High
1: Active Low
HS Polarity 0: Active High
1: Active Low
DE Polarity 0: Active High
1: Active Low
FRC2
Enable
0: FRC2 Disable
1: FRC2 Enable
FRC1
Enable
0: FRC1 Disable
1: FRC1 Enable
Hi-FRC 2
Disable
0: Hi-FRC2 Enable
1: Hi-FRC2 Disable
Hi-FRC 1
Disable
0: Hi-FRC1 Enable
1: Hi-FRC1 Disable
0x00 Page
Setting
00: Configuration Registers
01: Red LUT
10: Green LUT
11: Blue LUT
White
Balance
Enable
0: White Balance Disable
1: White Balance Enable
LUT Reload 0: Reload Disable
Enable
1: Reload Enable
Reserved
40
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS90UH926Q-Q1