DS90UH926Q-Q1 Datasheet, PDF (23/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

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DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance
LUT, and is intended to be used when 24-bit data is being driven to an 18-bit display with a white balance LUT
that is calibrated for an 18-bit data source. The second FRC block, FRC2, follows the white balance block and is
intended to be used when fine adjustment of color temperature is required on an 18-bit color display, or when a
24-bit source drives an 18-bit display with a white balance LUT calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to DS90UH926Q-Q1 control registers through
the serial bus interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off sub-
pixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 18. The 1 or 0 value shown in the table
describes whether the 6-bit value is increased by 1 (1) or left unchanged (0). In this case, the 3 truncated LSBs
are 001.
F0L0
PD1
Cell Value 010
LSB=001
Frame = 0, Line = 0
Pixel Data one
R[7:2]+0, G[7:2]+1, B[7:2]+0
three lsb of 9 bit data (8 to 9 for Hi-Frc)
Pixel Index PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
LSLBS=B00=1001
F0L0
010
000
000
000
000
000
010
000
F0L1
101
000
000
000
101
000
000
000
F0L2
000
000
010
000
010
000
000
000
F0L3
000
000
101
000
000
000
101
000
F1L0
F1L1
F1L2
F1L3
000
000
000
000
000
000
000
000
000
111
000
000
000
111
000
000
000
000
000
000
000
000
000
000
000
000
000
111
000
000
000
111
F2L0
F2L1
F2L2
F2L3
000
000
010
000
010
000
000
000
000
000
101
000
000
000
101
000
010
000
000
000
000
000
010
000
101
000
000
000
101
000
000
000
F3L0
F3L1
F3L2
F3L3
000
000
000
000
000
000
000
000
000
000
000
111
000
000
000
111
000
000
000
000
000
000
000
000
000
111
000
000
000
111
000
000
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
R = 4/32
G = 4/32
B = 4/32
Figure 18. Default FRC Algorithm
SOURCE
24–bit
24–bit
24–bit
18–bit
Table 4. Recommended FRC Settings
WHITE BALANCE LUT
24–bit
24–bit
18–bit
24–bit
DISPLAY
24–bit
18–bit
18–bit
24–bit
FRC1
Disabled
Disabled
Enabled
Disabled
FRC2
Disabled
Enabled
Disabled
Disabled
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