DS90UH926Q-Q1 Datasheet, PDF (24/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
SOURCE
18–bit
18–bit
Table 4. Recommended FRC Settings (continued)
WHITE BALANCE LUT
24–bit
18–bit
DISPLAY
18–bit
18–bit
FRC1
Disabled
Disabled
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FRC2
Enabled
Disabled
7.3.17 Internal Pattern Generation
The DS90UH926Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual
verification of panel operation. As long as the device is not in power down mode, the test pattern will be
displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a
programmed oscillator frequency. For detailed information, refer to AN-2198 Exploring the Internal Test Pattern
Generation Feature of 720p FPD-Link III Devices (SNLA132).
7.3.18 I2S Receiving
In normal 24-bit RGB operation mode, the DS90UH926Q-Q1 provides up to 3-bit of I2S. They are I2S_CLK,
I2S_WC and I2S_DA, as well as the Master I2S Clock (MCLK). The encrypted and packetized audio information
is received during the video blanking periods along with specific information about the clock frequency. The bit
rates of any I2S input bits must maintain one fourth of the PCLK rate. The audio decryption is supported per
HDCP v1.3. A jitter cleaning feature reduces I2S_CLK output jitter to ±2ns.
7.3.18.1 I2S Jitter Cleaning
The DS90UH926Q-Q1 features a standalone PLL to clean the I2S data jitter supporting high end car audio
systems. If I2S CLK frequency is less than 1 MHz, this feature has to be disabled through the register bit I2S
Control (0x2B) in Table 11.
7.3.18.2 Secondary I2S Channel
In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio
channel in additional to the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this
synchronization feature on this bit, set the MODE_SEL (Table 9) or program through the register bit (Table 11).
7.3.18.3 MCLK
The deserializer has an I2S Master Clock Output. It supports x1, x2, or x4 of I2S CLK Frequency. When the I2S
PLL is disabled, the MCLK output is OFF. Table 5 below covers the range of I2S sample rates and MCLK
frequencies.
By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK frequencies can also
be enabled through the register bit [7:4] (I2S MCLK Output) of 0x3A shown in Table 11. To select desired MCLK
frequency, write bit 7 (0x3A) = 1, then write to bit [6:4] accordingly.
SAMPLE RATE
(kHz)
32
44.1
48
Table 5. Audio Interface Frequencies
I2S DATA WORD SIZE
(bits)
16
16
16
I2S CLK
(MHz)
1.024
1.411
1.536
MCLK OUTPUT
(MHz)
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
x1 of I2S CLK
x2 of I2S CLK
x4 of I2S CLK
BIT [6:4]
(ADDRESS 0x3A)
000
001
010
000
001
010
000
001
010
24
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