DS90UH926Q-Q1 Datasheet, PDF (29/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

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DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
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1:3 Repeater
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Figure 20. HDCP Maximum Repeater Application
To support HDCP Repeater operation, the DS90UH926Q-Q1 Deserializer includes the ability to control the
downstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV
list to the upstream HDCP Transmitter. An I2C master within the DS90UH926Q-Q1 communicates with the I2C
slave within the DS90UH925Q-Q1 Serializer. The DS90UH925Q-Q1 Serializer handles authenticating with a
downstream HDCP Receiver and makes status available through the I2C interface. The DS90UH926Q-Q1
monitors the transmit port status for each DS90UH925Q-Q1 and reads downstream KSV and KSV list values
from the DS90UH925Q-Q1.
In addition to the I2C interface used to control the authentication process, the HDCP Repeater implementation
includes two other interfaces. A parallel LVCMOS interface provides the unencrypted video data in 24-bit RGB
format and includes the DE/VS/HS control signals. In addition to providing the RGB video data, the parallel
LVCMOS interface communicates control information and packetized audio data during video blanking intervals.
A separate I2S audio interface may optionally be used to send I2S audio data between the HDCP Receiver and
HDCP Transmitter in place of using the packetized audio over the parallel LVCMOS interface. All audio and
video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP Transmitter.
Figure 21 provides more detailed block diagram of a 1:2 HDCP repeater configuration.
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