DS90UH926Q-Q1 Datasheet, PDF (48/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
Typical Application (continued)
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HOST
Graphics
Processor
V_DDIO VDD33
(1.8V or 3.3V) (3.3V)
V_DD33 V_DDIO
(3.3V) (1.8V or 3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
3
I2S AUDIO _/
(STEREO)
SCL
SDA
IDx
DOUT+
FPD-Link III
1 Pair /AC Coupled
0.1 2F
0.1 2F
DOUT-
DS90UH925Q-Q1
Serializer
DAP
100 ohm STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UH926Q-Q1
Deserializer
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
3
/
I2S AUDIO
(STEREO)
MCLK
RGB Display
720p
24-bit color depth
DAP
Figure 25. Typical Display System Diagram
8.2.1 Design Requirements
For the typical design application, use the following as input parameters:
Table 12. Design Parameters
DESIGN PARAMETER
VDDIO
VDD33
AC Coupling Capacitor for RIN±
PCLK Frequency
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
100 nF
78 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Transmission Media
The DS90UH925Q-Q1 and DS90UH926Q-Q1 chipset is intended to be used in a point-to-point configuration
through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize
impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should
have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the
quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical
environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the
application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye opening width and eye opening height. A differential probe should be used to measure
across the termination resistor at the CMLOUT± pin Figure 2.
48
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