DS90UH926Q-Q1 Datasheet, PDF (14/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
SDA
t_f
SCL
START
t_LOW
t_r
t_f
t_HD;STA
t_SP
t_r
t_BUF
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
REPEATED
START
t_SU;STO
STOP START
Figure 9. Serial Control Bus Timing Diagram
6.10 Typical Characteristics
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Time (1.25 ns/DIV)
NOTE: On the rising edge of each clock period, the CML driver
outputs a low Stop bit, high Start bit, and 33 DC-scrambled data
bits.
Figure 10. Serializer CML Driver Output
With 78 MHZ TX Pixel Clock
78 MHz TX
Pixel Clock
Input
(2 V/DIV)
78 MHz RX
Pixel Clock
Output
(2 V/DIV)
Time (10 ns/DIV)
Figure 11. Comparison of Deserializer LVCMOS RX PCLK
Output Locked to a 78-MHz TX PCLK
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