DS90UH926Q-Q1 Datasheet, PDF (20/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
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Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal Mode -
check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 15. BIST Mode Flow Diagram
7.3.15.2 Forward-Channel and Back-Channel Error Checking
While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero
pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to
the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-
zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The
deserializer then outputs a SSO pattern on the RGB output pins.
The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as
indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The
register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the
functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in
BIST mode only and keeps the record of last BIST run until it clears or enters BIST mode again.
BISTEN
(DES)
PCLK
(RFB = L)
ROUT[23:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
DATA
(internal)
PASS
Prior Result
Normal
SSO
X = bit error(s)
X
X
X
BIST Test
BIST Duration
Figure 16. BIST Waveforms
PASS
FAIL
BIST
Result
Held
Normal
20
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