DS90UH926Q-Q1 Datasheet, PDF (17/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

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DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
Feature Description (continued)
7.3.7 EMI Reduction Features
7.3.7.1 Spread Spectrum Clock Generation (SSCG)
The DS90UH926Q-Q1 provides an internally-generated spread spectrum clock (SSCG) to modulate its outputs.
Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.5%
(5% total) at up to 100-kHz modulations are available. This feature may be controlled by register. See Table 1,
Table 2 and Table 11. Do not enable the SSCG feature if the source PCLK into the SER has a clock with spread
spectrum already.
Frequency
F_PCLK+
F_PCLK
F_PCLK-
fdev(max)
fdev(min)
Time
1/fmod
Figure 14. SSCG Waveform
Table 1. SSCG Configuration
LFMODE = L (15 - 85 MHz)
SSCG CONFIGURATION (0x2C) LFMODE = L (15 - 85 MHz)
SSC[2]
SSC[1]
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC[0]
L
H
L
H
L
H
L
H
SPREAD SPECTRUM OUTPUT
Fdev (%)
±0.9
±1.2
±1.9
±2.5
±0.7
±1.3
±2.0
±2.5
Fmod (kHz)
PCLK / 2168
PCLK / 1300
Table 2. SSCG Configuration
LFMODE = H (5 - <15 MHz)
SSCG CONFIGURATION (0x2C) LFMODE = H (5 - <15 MHz)
SSC[2]
SSC[1]
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC[0]
L
H
L
H
L
H
L
H
SPREAD SPECTRUM OUTPUT
Fdev (%)
±0.5
±1.3
±1.8
±2.5
±0.7
±1.2
±2.0
±2.5
Fmod (kHz)
PCLK / 628
PCLK / 388
7.3.8 Enhanced Progressive Turn-On (EPTO)
The deserializer LVCMOS parallel outputs timing are delayed. Groups of 8-bit R, G and B outputs switch in a
different time. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise.
In addition it spreads the noise spectrum out reducing overall EMI.
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