DS90UH926Q-Q1 Datasheet, PDF (18/58 Pages) Texas Instruments – 720p 24-Bit Color FPD-Link III Deserializer With HDCP

DS90UH926Q-Q1
SNLS337K – OCTOBER 2010 – REVISED JANUARY 2015
www.ti.com
7.3.9 LVCMOS VDDIO Option
The deserializer parallel bus can operate with 1.8-V or 3.3-V levels (VDDIO) for target (Display) compatibility.
The 1.8-V levels will offer a lower noise (EMI) and also a system power savings.
7.3.10 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the V_DDIO, where V_DDIO = 3.0V to 3.6V or V_DD33. To save power disable the link when the display
is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after V_DD33 and V_DDIO
have reached final levels; no external components are required. In the case of driven by the V_DDIO = 3.0 V to 3.6
V or V_DD33 directly, a 10-kΩ resistor to the V_DDIO = 3.0 V to 3.6 V or V_DD33 , and a >10-µF capacitor to the ground
are required (See Figure 24).
7.3.11 Stop Stream Sleep
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer will
then lock to the incoming signal and recover the data.
NOTE
In STOP STREAM SLEEP, the Serial Control Bus Registers values are retained.
7.3.12 Serial Link Fault Detect
The serial link fault detection is able to detect any of following 7 conditions
1. cable open
2. + to - short
3. + short to GND
4. - short to GND
5. + short to battery
6. - short to battery
7. Cable is linked incorrectly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control
Bus Register bit 0 of address 0x1C Table 11. The link errors can be monitored though Link Error Count of the
Serial Control Bus Register bit [4:0] of address 0x41 Table 11.
7.3.13 Oscillator Output
The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature is controlled by
register Address 0x02, bit 5 (OSC Clock Enable). See Table 11.
7.3.14 Pixel Clock Edge Select (RFB)
The RFB determines the edge that the data is strobed on. If RFB is High (‘1’), output data is strobed on the
Rising edge of the PCLK. If RFB is Low (‘0’), data is strobed on the Falling edge of the PCLK. This allows for
inter-operability with downstream devices. The deserializer output does not need to use the same edge as the
Ser input. This feature may be controlled by register. See Table 11.
7.3.15 Built In Self Test (BIST)
An optional At-Speed, Built-In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics. The BIST is not available in backwards-compatible mode.
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