SMJ320C31_07 Datasheet, PDF (9/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
functional block diagram
Cache
(64 × 32)
32 24
RAM
Block 0
(1K × 32)
24
32
RAM
Block 1
(1K × 32)
24
32
ÉÉÉÉ₂₄ÉÉÉÉ_LÉÉÉÉ_Boaodo3et2ÉÉÉÉ_r ÉÉÉÉ
RDY
HOLD
HOLDA
STRB
R/W
D31− D0
A23 − A0
PDATA Bus
PADDR Bus
DDATA Bus
DADDR1 Bus
DADDR2 Bus
DMADATA Bus
DMAADDR Bus
32 24
32 24 24
32
24
IR
PC
RESET
INT(3 − 0)
IACK
MCBL / MP
XF(1,0)
VDD(19 − 0)
VSS(24 − 0)
X1
X2 / CLKIN
H1
H3
EMU(3 − 0)
MUX
DMA Controller
Global-Control
Register
CPU1
CPU2
REG1
REG2
32
32 40
40
Multiplier
40
32-Bit
Barrel
Shifter
ALU
40
40
Extended-
Precision
32
Registers
(R7−R0)
Source-Address
Register
Destination-
Address
Register
Transfer-
Counter
Register
40
40
40
DISP0, IR0, IR1
ARAU0 _BK ARAU1
24
24
24
Auxiliary
24
32
Registers
(AR0 − AR7)
32
32
32
Other
32
32
Registers
(12)
Serial Port 0
Serial-Port-Control
Register
Receive/Transmit
(R / X) Timer Register
Data-Transmit
Register
Data-Receive
Register
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
Timer 0
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
Timer 1
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
Port Control
STRB-Control
Register
TCLK0
TCLK1
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
9