SMJ320C31_07 Datasheet, PDF (31/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
interrupt response timing
The following table defines the timing parameters for the INT signals.
timing for INT3−INT0 response (see Figure 24)
NO.
50 tsu(INT-H1L) Setup time, INT3−INT0 before H1 low
51 tw(INT)
Pulse duration, interrupt to ensure
only one interrupt
† _{P = tc(H)}
* This parameter is not production tested.
’C31-40
MIN MAX
13
P 2P†*
’LC31-40
MIN MAX
15
P 2P†*
’C31-50
MIN MAX
11
P 2P†*
’C31-60
MIN MAX
8
P 2P†*
UNIT
ns
ns
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
SMJ320C3x interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA
respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
D A minimum of one H1 falling edge
D No more than two H1 falling edges
The SMJ320C3x can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 24 occurs; otherwise, an additional delay
of one clock cycle is possible.
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