SMJ320C31_07 Datasheet, PDF (21/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
memory read/write timing
The following table defines memory read/write timing parameters for STRB.
timing parameters for memory (STRB = 0) read/write (see Figure 14 and Figure 15)^†
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
MIN MAX MIN MAX MIN MAX
12 td(H1L-SL)
Delay time, H1 low to STRB low
13 td(H1L-SH)
Delay time, H1 low to STRB high
14 td(H1H-RWL)R Delay time, H1 high to R/W low (read)
15 td(H1L-A)
Delay time, H1 low to A valid
16 tsu(D-H1L)R
Setup time, D before H1 low (read)
17 th(H1L-D)R
Hold time, D after H1 low (read)
18 tsu(RDY-H1H)
Setup time, RDY before H1 high
19 th(H1H-RDY)
Hold time, RDY after H1 high
20 td(H1H-RWH)W Delay time, H1 high to R/W high (write)
21 tv(H1L-D)W
Valid time, D after H1 low (write)
22 th(H1H-D)W
Hold time, D after H1 high (write)
23 td(H1H-A)W
Delay time, H1 high to A valid on back-to-back
write cycles (write)
0*
6
0*
5
0*
5
0*
6
0*
5
0*
5
0*
9
0*
7
0*
6
0*
10
0*
10
0*
8
14
10
9
0
0
0
8
6
5
0
0
0
9
7
6
17
14
12
0
0
0
15
14
10
24 td(A-RDY)
Delay time, RDY from A valid
7*
6*
6*
† _{See Figure 16 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (CT = 80 pF).}
* This parameter is not production tested.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
H3
H1
12
13
STRB
R/W
15
14
A
24
D
18
16
17
19
RDY
NOTE A: STRB remains low during back-to-back read operations.
Figure 14. Timing for Memory (STRB = 0) Read
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