SMJ320C31_07 Datasheet, PDF (24/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
XF0 timing when executing STFI and STII^†
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.
timing for XF0 when executing STFI or STII (see Figure 18)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
MIN MAX MIN MAX MIN MAX
28 td(H3H-XF0H) Delay time, H3 high to XF0 high
13
12
11 ns
† _{XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of}
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
Fetch
STFI or STII
H3
Decode
Read
Execute
H1
STRB
R/W
A
D
RDY
28
XF0 Pin
Figure 18. Timing for XF0 When Executing an STFI or STII
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