SMJ320C31_07 Datasheet, PDF (7/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
Terminal Functions
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
TERMINAL
TYPE†
NAME
QTY
DESCRIPTION
CONDITIONS
WHEN
SIGNAL IS Z TYPE‡
PRIMARY-BUS INTERFACE
D31 −D0
32 I / O / Z 32-bit data port
S
H
R
A23 −A0
24
O / Z 24-bit address port
S
H
R
R/W
Read / write. R/ W is high when a read is performed and low when a write is performed
1
O / Z _{over the parallel interface.}
S
H
R
STRB
1
O / Z External-access strobe
S
H
RDY
Ready. RDY indicates that the external device is prepared for a transaction
1
I
completion.
HOLD
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23 −A0,
1
I
D31 −D0, STRB, and R / W are placed in the high-impedance state and all transac-
tions over the primary-bus interface are held until HOLD becomes a logic high or until
the NOHOLD bit of the primary-bus-control register is set.
HOLDA
Hold acknowledge. HOLDA is generated in response to a logic low on HOLD. HOLDA
1
O/Z
indicates that A23 −A0, D31 −D0, STRB, and R / W are in the high-impedance state
and that all transactions over the bus are held. HOLDA is high in response to a logic
S
high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
CONTROL SIGNALS
RESET
1
I
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset vector.
INT3 −INT0
4
I External interrupts
IACK
1
O/Z
Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate the beginning or the end of an interrupt-service routine.
S
MCBL / MP
1
I Microcomputer boot-loader / microprocessor mode-select
SHZ
Shutdown high impedance. When active, SHZ shuts down the device and places all
pins in the high-impedance state. SHZ is used for board-level testing to ensure that
1
I no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory
and register contents. Reset the device with SHZ high to restore it to a known
operating condition.
XF1, XF0
2
I/O/Z
External flags. XF1 and XF0 are used as general-purpose I / Os or to support
interlocked processor instruction.
S
R
SERIAL PORT 0 SIGNALS
CLKR0
1
I / O / Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S
R
CLKX0
1
I/O/Z
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter.
S
R
DR0
1
I / O / Z Data-receive. Serial port 0 receives serial data on DR0.
S
R
DX0
1
I / O / Z Data-transmit output. Serial port 0 transmits serial data on DX0.
S
R
FSR0
1
I/O/Z
Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0.
S
R
FSX0
1
I/O/Z
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0.
S
R
TIMER SIGNALS
TCLK0
1
I/O/Z
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an
output, TCLK0 outputs pulses generated by timer 0.
S
TCLK1
1
I/O/Z
Timer clock 1. As an input, TCLK0 is used by timer 1 to count external pulses. As an
output, TCLK1 outputs pulses generated by timer 1.
S
† _{I = input, O = output, Z = high-impedance state}
‡ _{S = SHZ active, H = HOLD active, R = RESET active}
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