SMJ320C31_07 Datasheet, PDF (30/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
RESET timing (continued)
CLKIN
38
RESET
(see Notes A and B)
39
40
41
H1
42
H3
D
(see Note C)
A
(see Note C)
Control Signals
(see Note D)
Ten H1 Clock Cycles
44
43
45
46
47
SMJ320C31 R/W
(see Note E)
48
IACK
Asynchronous
49
Reset Signals
(see Note A)
NOTES: A. Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
C. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the
reset vector is fetched twice, with no software wait states.
D. Control signals include STRB.
E. The R/W outputs are placed in a high-impedance state during reset and can be provided with a resistive pullup, nominally
18−22 kΩ, if undesirable spurious writes are caused when these outputs go low.
Figure 23. Timing for RESET
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