SMJ320C31_07 Datasheet, PDF (42/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
changing the peripheral pin I/O modes
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa.
timing requirements for peripheral pin changing from general-purpose output to input mode
(see Note 6 and Figure 30)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
MIN MAX MIN MAX MIN MAX
84 th(H1H)
Hold time, peripheral pin after H1 high
13
10
8 ns
85 tsu(GPIO-H1L) Setup time, peripheral pin before H1 low
9
9
8
ns
86 th(H1L-GPIO) Hold time, peripheral pin after H1 low
0
0
0
ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Execution
of Store of
Peripheral-
Control
Register
H3
Buffers Go
From
Output to
Input
Synchronizer Delay
Value on Pin
Seen in
Peripheral-
Control
Register
H1
I/O
Control Bit
84
Peripheral
Pin
Output
(see Note A)
Data Bit
85
86
Data
Sampled
Data
Seen
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 30. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
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