SMJ320C31_07 Datasheet, PDF (29/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
RESET timing (see Figure 23)
’C31-40
NO.
MIN MAX
38 tsu(RESET-CIL)
Setup time, RESET before
CLKIN low
10 P†*
39 td(CLKINH-H1H)
Delay time, CLKIN high to
H1 high (see Note 4)
2 14
40 td(CLKINH-H1L)
Delay time, CLKIN high to
H1 low (see Note 4)
2 14
Setup time, RESET high
41 tsu(RESETH-H1L)
before H1 low and after ten
9
H1 clock cycles
42 td(CLKINH-H3L)
Delay time, CLKIN high to
H3 low (see Note 4)
2 14
43 td(CLKINH-H3H)
Delay time, CLKIN high to
H3 high (see Note 4)
2 14
44 tdis(H1H-DZ)
Disable time, H1 high to D
(high impedance)
15*
Disable time, H3 high to A
45 tdis(H3H-AZ)
(high impedance)
9*
46 td(H3H-CONTROLH)
Delay time, H3 high to
control signals high
9*
47 td(H1H-RWH)
Delay time, H1 high to R/W
high
9*
Delay time, H1 high to IACK
48 td(H1H-IACKH)
high
9*
Disable time, RESET low to
49 tdis(RESETL-ASYNCH) asynchronous reset signals
21*
disabled (high impedance)
† _{P = tc(CI)}
* This parameter is not production tested.
NOTE 4: See Figure 12 and Figure 13 for typical temperature dependence.
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
’LC31-40
MIN MAX
10 P†*
’C31-50
MIN MAX
10 P†*
’C31-60
MIN MAX
7 P†*
UNIT
ns
2 14
2 10
2 10 ns
2 14
2 10
2 10 ns
9
7
6
ns
2 14
2 14
13*
9*
9*
9*
9*
2 10
2 10
12*
8*
8*
8*
8*
2 10 ns
2 10 ns
11* ns
7* ns
7* ns
7* ns
7* ns
21*
17*
14* ns
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