SMJ320C31_07 Datasheet, PDF (34/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
serial-port timing for SMJ320C31-40 and SMJ320LC31-40 (see Figure 26 and Figure 27)
NO.
54 td(H1H-SCK)
55 tc(SCK)
Delay time, H1 high to internal CLKX/R
Cycle time, CLKX/R
CLKX/R ext
CLKX/R int
56 tw(SCK)
Pulse duration, CLKX/R high/low
CLKX/R ext
CLKX/R int
57 tr(SCK)
58 tf(SCK)
59 td(C-DX)
Rise time, CLKX/R
Fall time, CLKX/R
Delay time, CLKX to DX valid
CLKX ext
CLKX int
60 tsu(DR-CLKRL) Setup time, DR before CLKR low
CLKR ext
CLKR int
61 th(CLKRL-DR)
Hold time, DR from CLKR low
CLKR ext
CLKR int
62 td(C-FSX)
Delay time, CLKX to internal FSX high/low
CLKX ext
CLKX int
63 tsu(FSR-CLKRL) Setup time, FSR before CLKR low
CLKR ext
CLKR int
64 th(SCKL-FS)
Hold time, FSX/R input from CLKX/R low
CLKX/R ext
CLKX/R int
65 tsu(FSX-C)
Setup time, external FSX before CLKX
CLKX ext
CLKX int
66 td(CH-DX)V
Delay time, CLKX to first DX bit, FSX
precedes CLKX high
CLKX ext
CLKX int
67 td(FSX-DX)V
68 td(CH-DXZ)
Delay time, FSX to first DX bit, CLKX precedes FSX
Delay time, CLKX high to DX high impedance following last data
bit
* This parameter is not production tested.
’C31-40
’LC31-40
MIN
MAX
13
tc(H)x2.6
tc(H)x2
tc(H)+10
[tc(SCK)/2]−5
tc(H)x2³²
[tc(SCK)/2]+5
7
7
30
17
9
21
9
0
27
15
9
9
9
0
−[tc(H)−8]*
[tc(H)−21]*
[tc(SCK)/2]−10*
tc(SCK)/2*
30*
18*
30*
17*
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
34
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