SMJ320C31_07 Datasheet, PDF (41/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The table, timing parameters for peripheral pin general-purpose I/O, defines peripheral pin general-purpose I/O
timing parameters.
timing requirements for peripheral pin general-purpose I/O (see Note 6 and Figure 29)
NO.
’C31-33
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
81
tsu(GPIO-H1L)
Setup time, general-purpose input
before H1 low
12
10
9
8
ns
Hold time, general-purpose input after
82 th(H1L-GPIO) _{H1 low}
0
0
0
0
ns
83
td(H1H-GPIO)
Delay time, general-purpose output
after H1 high
15
13
10
8 ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
H3
H1
82
81
83
83
Peripheral
Pin
(see Note A)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 29. Timing for Peripheral Pin General-Purpose I/O
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