SMJ320C31_07 Datasheet, PDF (44/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers.
The following tables define the timing requirements for the timer pin.
timing for timer pin (see Figure 32 and Note 7)
’C31-40,
’LC31-40
’C31-60
NO.
’C31-50
UNIT
MIN
MAX
MIN
MAX
88
tsu(TCLK-H1L)
Setup time, TCLK external
before H1 low
10
6
ns
Hold time, TCLK external after
89 th(H1L-TCLK) _{H1 low}
0
0
ns
90
td(H1H-TCLK)
Delay time, H1 high to TCLK
internal valid
9
8
ns
91 tc(TCLK)
Cycle time, TCLK
TCLK ext
TCLK int
tc(H)×2.6
tc(H)×2
tc(H)×2³²*
tc(H)×2.6
tc(H)×2
ns
tc(H)×2³²*
92 tw(TCLK)
Pulse duration,
TCLK high/low
TCLK ext
tc(H)+10
tc(H)+10
ns
TCLK int [tc(TCLK)/2]−5 [tc(TCLK)/2]+5 [tc(TCLK)/2]−5 [tc(TCLK)/2]+5
NOTE 7: Numbers 88 and 89 are applicable for a synchronous input clock. Timing parameters 91 and 92 are applicable for an asynchronous
input clock.
* This parameter is not production tested.
H3
H1
89
90
88
90
Peripheral
Pin
(see Note A)
92
91
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 32. Timing for Timer Pin
44
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