SMJ320C31_07 Datasheet, PDF (23/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
XF0 and XF1 timing when executing LDFI or LDII
The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII.
timing for XF0 and XF1 when executing LDFI or LDII for SMJ320C31 (see Figure 17)
NO.
25 td(H3H-XF0L) Delay time, H3 high to XF0 low
26 tsu(XF1-H1L) Setup time, XF1 before H1 low
27 th(H1L-XF1) Hold time, XF1 after H1 low
’C31-40
MIN MAX
13
9
0
’LC31-40
MIN MAX
13
10
0
’C31-50
MIN MAX
12
8
0
’C31-60
MIN MAX
11
8
0
UNIT
ns
ns
ns
Fetch
LDFI or LDII
Decode
H3
Read
Execute
H1
STRB
R/W
A
D
RDY
25
XF0 Pin
26
27
XF1 Pin
Figure 17. Timing for XF0 and XF1 When Executing LDFI or LDII
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
23