SMJ320C31_07 Datasheet, PDF (33/59 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
timing for IACK (see Note 5 and Figure 25)
’C31-40
NO.
’LC31-40
’C31-50
’C31-60
UNIT
MIN MAX MIN MAX MIN MAX
52 td(H1H-IACKL) Delay time, H1 high to IACK low
9
7
6 ns
53 td(H1H-IACKH) Delay time, H1 high to IACK high
9
7
6 ns
NOTE 5: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode
phase of the IACK instruction is extended.
Fetch IACK
Instruction
H3
Decode IACK
Instruction
IACK Data
Read
H1
52
53
IACK
ADDR
Data
Figure 25. Timing for IACK
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